Smc-networks SMC91C95 User Manual download pdf (Page 88)

8028h - Extended Status Register(ESR)

7 6 5 4 3 2 1 0

RINGEVENT RINGENABLE

0 0 0 0 0 0 0 0

RINGEVENT: This bit is latched to a one at the

start of each ring frequency cycle (input from

ring input from modem, the MRINGIN signal

going high). When this bit and RINGENABLE

are both set to a one (1), the Changed bit in the

MCSR is set to a one(1). This bit is reset if the

host writes a one (1) and the change bit in the

MCSR register is unaffected if the host writes a

zero (0).

RINGENABLE: When set, this bit gates the

RINGEVENT into the Changed bit.

1 2 ... 83 84 85 86 87 88 89 90 91 92 93 ... 138 139

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Smc-networks SMC91C95 User Manual Page 88